Generally, a word line driver of a semiconductor memory device uses a high voltage VPP which is higher than a power supply voltage VDD, and a driving signal, which drives the word line driver, swings between the power supply voltage VDD and a ground voltage VSS, while the word line driver needs a swing voltage level between the high voltage VPP and the power supply voltage VDD. In the case where these two circuits (that is, power supply and word line driver) are directly coupled to each other without a level conversion circuit, leakage current can be caused in the circuit that uses the high voltage VPP. Therefore, a level shifter must be disposed between these two circuits.
FIG. 1 is a circuit diagram illustrating a conventional level shifter. In FIG. 1, the reference numerals VDDL and VDDH denote a low voltage level and a high voltage level, respectively. In the conventional semiconductor memory device, the low voltage level VDDL may be a low voltage VDD and the high voltage level VDDH may be a power supply voltage VDD.
In FIG. 1, a signal INb swings between the low voltage VDDL and the ground voltage VSS and a level shifter circuit is added in order to change the signal INb into a signal which swings between the high voltage VDDH and the ground voltage VSS.
A problem of the conventional level shifter will be explained shortly. First, when the input signal INb of the level shifter transits from a low level to a high level, a NMOS transistor mn1 is turned on and a NMOS transistor mn2 is turned off. A voltage level on a node AA drops to the ground voltage VSS through the NMOS transistor mn1 which is turned on. At this time, a PMOS transistor mp2 is turned on so that a node BB transits to a high voltage level and a conflict occurs between a PMOS transistor mp1 and the NMOS transistor mn1 before the PMOS transistor mp1 is turned off. Further, when the input signal INb transmits from a high voltage level to a low voltage level, a conflict occurs between the PMOS transistor mp2 and the NMOS transistor mn2.
When the drivability of the PMOS transistor is lower than that of the NMOS transistor, a normal operation is not guaranteed. Accordingly, the current drivability of the NMOS transistors is to be reinforced by increasing the size of the NMOS transistors in order to make the level shifter stable and fast. However, there is a limitation of the reinforcement of the drivability of the NMOS transistors with such a size increment as the input signal INb becomes lower and lower up to the threshold voltage of the NMOS transistors mn1 and mn2.
As mentioned above, the conventional level shifter circuit has a limitation of the current drivability which can be reinforced by increasing the size of the NMOS transistors when the input signal INb has a low voltage level.